Design And Simulation Of A Finite State Machine Suitable For Micro-Code Execution

ABSTRACT

Digital processors are built from very large scale integration circuits and the software to design them is only available to the manufacturers themselves. There is a need to design a central processing unit using large, medium and small scale integration circuits which can be used as a teaching aid in computer architecture and design. In this thesis a simulation model of a digital processor is designed using arithmetic logic unit, control unit and registers as building blocks with their interconnections. The presented digital processor is a 4-bit, 80 MHz incorporating sixteen instructions. The modules for the central processing unit were built from large, medium and small scale transistor transistor logic integrated circuits. The design and simulation is based on Electronic workbench software. The circuit is capable of modeling the functional and timing behavior of the digital processor to use instructions in the groups of data transfer, arithmetic, logical, bit manipulation, shift and program control. A state machine control unit was used for sequencing of the instructions. The clock pulses were supplied by a 555 timer instead of a quartz crystal in order to make it possible to vary the frequency to maximum by use of different values of capacitance and resistances. The results of frequency against different values of resistances were also plotted; this was carried out in order to calculate the optimum simulation time for different instructions. A set of four switches was used for selecting up of the opcodes and imputing data to the digital processor through the input port. Four probes were used to indicate the status of the registers, memory unit and the output port. In order to implement program control a conditional jump instruction is implemented when the state of the status register is logic 1. The mnemonic codes were also simulated and the results were found to be in agreement with theoretical values. With the sixteen opcodes, circuits for subtraction, addition and multiplication were simulated. The circuits yielded good data validity at the frequency of operation. Further work can be carried out in order to improve the processor to handle large amounts of data by using 8-bit and 16-bit registers. Five or six bit length opcodes could also increase the number of instructions to be executed from sixteen. Verilog hardware descriptive language and Very high speed hardware descriptive language can be used since they offer more tools for design.