Designing A Runtime Simulator For Queue Core Processor

ABSTRACT

In today’s era of modern architectures, high performance computing has received a lot of attention from diverse architectural levels. The performance crises in the computing arena have forced researchers to look for alternative architectures that will foster high performance whiles minimizing tradeoffs. The Queue Core processor is a novel 32-bit microprocessor that emerged as a result of the urgent desire for high performance microprocessor. The advent of the Queue Core processor has curb the performance crises due to its interesting features such as high Instruction Level Parallelism (ILP), dense program size, low power consumption, and elimination register concept. However, the demand in further improving the performance of the Queue Core processor has consequently triggered the growth in complexity. This has imposed a lot of constraints on the evaluation of Queue Processor with regards to timing, computations etc. Understanding of the internal dynamic mechanisms of the Queue Core Processor and their design space exploration therefore rely extensively on simulation tools which are traditionally software. In this research, we propose QSIM, a trace-driven and runtime simulator for the Queue Core processor. In QSIM, only a subset of the Queue Core Instruction Set Architecture has been implemented using the JAVA programming language. It is interesting to mention that this research work falls in the cross-road of two different domains: System Architecture and Software Engineering. The research will therefore be accomplished using methodical approach through the competent background knowledge of the Queue Core system architecture and application of Software Engineering principles. The advents of the QSIM amongst other benefits will principally offer an attractive opportunity to quickly evaluate the performance of the Queue Core Processor and serves as a tool to explore more Queue computation.